This invention relates to electronic phase detector circuits and more particularly to phase detector circuits suitable for use in phase-locked loops.
Phase-locked loop oscillators have many applications wherein a local oscillator must be synchronized to a received signal. Typically, a phase-locked loop includes a phase detecting device, a voltage controlled oscillator and a feed-back circuit. The phase detecting device receives a reference data signal while simultaneously receiving a feed-back data signal. In response thereto, the phase detecting device generates phase detection signals having an average amplitude indicating the difference in phase between two data signals. The voltage controlled oscillator is coupled to receive the phase detection signal. In response thereto, the voltage controlled oscillator generates output signals having a frequency proportional to the magnitude of the phase detection signal. The output of the voltage controlled oscillator is used to form the feed-back data signal through a feed-back circuit.
Phase-locked loops are utilized, for example, to generate a control signal in synchronism with a reference signal. Synchronization between the control and reference signals is largely dependent upon the operational characteristics of the phase detector. This is because the phase detector controls the voltage controlled oscillator which changes its output frequency in response to the phase detection signal to correct errors indicated by the phase detection signal.
In the control circuitry of a solid state inverter or the like, it is often necessary to sense electrical waveforms in one circuit and then generate a control signal which accurately reflects the desired phase angle with respect to a reference signal. For example, in a variable speed constant frequency (VSCF) aircraft power system, it becomes necessary to force the output of the VSCF inverter into synchronism with an external power source. This permits momentary paralleling of the VSCF system with external power for a non-interrupted power transfer. It is necessary to control the error between the VSCF output waveform and the external supply to small values. Any error will result in unbalanced real power flow. For lightly loaded conditions, this could mean that negative power would flow out of the VSCF inverter and positive power would flow out of the external supply during paralleled operation. If such a condition exists, even for as long as a tenth of a second, then the VSCF DC link voltage may rise to unacceptable levels. Therefore, an accurate and relatively fast phase-locked loop is required.
U.S. Pat. No. 4,520,319, issued May 28, 1985 to Baker illustrates a phase detector which is suitable for use in a phase-locked loop of a control circuit of a VSCF power system. A second type of phase detector which may be used in the control circuitry of a VSCF power system is illustrated in the phase-locked loop Item No. 60 of FIG. 4 of a co-pending commonly assigned application Ser. No. 938,652, filed Dec. 5, 1986 by M. A. Beg D. E. Baker and entitled "Master Clock System for a Parallel Variable Speed Constant Frequency Power System" , now U.S. Pat. No. 4,707,142, issued Nov. 17, 1987.
These phase detectors meet the basic VSCF phase locked loop requirements that: phase-lock occurs when phase error between the input and output is zero degrees; at phase-lock output ripple voltage is zero, with deviations from zero phase error causing increasingly higher ripple until maximum ripple occurs at plus or minus 180.degree.; and only one stable point (zero output) exists over a 360.degree. span, thereby eliminating the possibility of phase lock at the wrong angle. Since ripple voltage is very nearly zero, no additional filtering is needed between the phase detector and the integrator of the phase-locked loop to reduce frequency modulation.
Although both of those phase detector circuits perform their intended function in a satisfactory manner, they possess certain characteristics which limit their utility. For example, the phase detector illustrated in Pat. No. 4,520,319 requires that the input frequency signal has a 50% duty cycle. This requirement may be difficult to meet if the frequency source is a zero crossing detector on an external power source. In that case, a complex debounce circuit may be required to maintain the 50% duty cycle and still accurately sense the input frequency. Although the phase detector circuit illustrated in Pat. No. 4,704,142 is less duty cycle dependent in that it does not rely on the falling edge of the input signals, it still requires that both signals be at a logic low state simultaneously. Also, since it utilizes AC coupled logic, it is susceptible to electromagnetic interference. It is therefore desirable to develope a phase detector circuit which does not utilize AC (capacitor) coupled logic and is not limited to input signals having a 50% duty cycle.